The present invention relates to a ferroelectric memory.
In recent years, there has been devised a ferroelectric memory in which a ferroelectric material is used in the capacitor of a memory cell so as to render stored data nonvolatile. Since the ferroelectric capacitor has a hysteresis property, a polarization of different polarity depending on the previous history remains even at zero electric field. The nonvolatile memory is implemented by representing stored data by means of a polarity remaining in the ferroelectric capacitor.
There are disclosed in U.S. Pat. No. 4,873,664 two types of ferroelectric memories. In the first-type memory, a memory cell consists of 1 transistor and 1 capacitor per bit (1T1C) so that 1 dummy memory cell (reference cell) is provided for every 256 main memory cells (normal cells), for example. In the second-type memory, on the other hand, a memory cell consists of 2 transistors and 2 capacitors per bit (2T2C) with the provision of no dummy memory cell so that a complementary pair of data is stored in a pair of ferroelectric capacitors.
Of ferroelectric materials for constituting capacitors, potassium nitrate (KNO.sub.3), PLZT (PbLa.sub.2 O.sub.3 --ZrO.sub.2 --TiO.sub.2), PZT (PbTiO.sub.3 --PbZrO.sub.3), and the like are well-known. According to PCT International Patent Publication No. WO93/12542, there is also known a ferroelectric material which presents extremely low fatigue compared with PZT, and hence is suitable for a ferroelectric memory.
In the above ferroelectric memory of 11C configuration according to U.S. Pat. No. 4,873,664, a dummy memory cell capacitor has a capacitance at least double the capacitance of a main memory cell capacitor, which means that the dummy memory cell capacitor occupies an area double the area occupied by the main memory cell capacitor. Moreover, in reading data from the main memory cell, the main memory cell capacitor is restored to its initial polarization state after the polarity is reversed or sustains its initial polarization state without reversing the polarity, depending on the data stored therein. On the other hand, the dummy memory cell capacitor is designed to sustain its original polarization state without reversing the polarity, irrespective of the data stored in the main memory cell. In other words, the voltage placed between the electrodes of the main memory cell capacitor alternates between the positive and negative polarities, while the voltage placed between the electrodes of the dummy memory cell capacitor remains either positive or negative. Each of the voltage applied to the cell plate electrode of the capacitor in the main memory cell, the voltage applied to the cell plate electrode of the capacitor in the dummy memory cell (dummy cell plate electrode), the voltage applied to the word line connected to the gate electrode of the main memory cell transistor, and the voltage applied to the word line connected to the gate electrode of dummy memory cell transistor (dummy word line) is 5 V, which is equal to the power-source voltage. Furthermore, regardless of the data stored in the main memory cell, the voltage of the word line and the voltage of the dummy word line are switched to the "L" state after the voltage of the cell plate electrode of the main memory cell capacitor was switched to the "L" state and the voltage of the cell plate electrode of the dummy memory cell capacitor is switched to the "L" state at the same time as the voltage of the word line and the voltage of the dummy word line are switched to the "L" state.
Thus, since the dummy memory cell capacitor is operated with a voltage which is constantly positive or negative in the conventional ferroelectric memory of 1T1C configuration, a significant change is caused in its hysteresis property during use due to the effect of a so-called imprint. Consequently, the operating margin of the ferroelectric memory is reduced, resulting in malfunction. Moreover, since the dummy memory cell capacitor which occupies an area several times larger than the area occupied by the main memory cell has been provided as the reference cell, there are variations in capacitance of the dummy memory cell capacitors manufactured, resulting in reduced operating margin.
If the power-source voltage is lowered, the charge resulting from the polarity remaining in a memory cell capacitor is reduced in each of the 1T1C memory and the 2T2C memory, also resulting in reduced operating margin. Furthermore, in restoring a logic voltage "H" to the memory cell capacitor, there occurs a so-called Vt reduction, wherein the voltage for restoring data to the memory cell capacitor is reduced to a value lower than the electric potential of the gate electrode of the memory cell transistor due to a threshold voltage Vt. As a result, the charge resulting from a residual polarization is reduced, thus reducing operating margin.